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Selection Guide for 25G Co-packaged Photonics for Island Applications

Jan 03, 2026

Electronic Chip Package and Co-Packaged Optics

Meanwhile, the optical module, enabled by silicon photonics, is now treated similarly to electronic chips, and advanced co-packaged optics (CPO) is

Apr 20, 2026

Co-Designed Silicon Photonics Chip I/O for Energy-Efficient Petascale

An urgent need arises for ultra–high-bandwidth and energy-eficient communica-tions among compute clusters to support the application demands. Embedded silicon photonics (SiPh) promises to enable

Jul 19, 2025

Co-Packaged Optics: Market and Technology Update

Co-Packaged Optics: Market and Technology Update The state of the CPO market and outlook for future progress.

Dec 24, 2025

SMoazeni_UW

This paper gives a brief overview of state-of-the-art of co-packaged optical I/O and requirements of its next generations. We also discuss ideas to exploit co-packaged optics in disaggregated AI systems

Dec 16, 2025

Co-packaged Optics

Co-packaged optics (CPO) are heterogeneous integration packaging methods to inte-grate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the

Jan 25, 2026

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New Investment Guide Focuses on Identifying Stocks That Can Multiply in Value by Ten Times or More OMAHA, Neb., Tue, Jul 7 2026 12:56 PM Book aims to level the playing field between institutional

Feb 10, 2026

Interfacing silicon photonics for high-density co

This article focuses on optical interfacing challenges for high-density co-packaged optics (CPO) applications.

Aug 02, 2025

Co-Designed Silicon Photonics Chip I/O for Energy-Efficient Petascale

In this work, we present our scalable DWDM link architecture, designed with co-packaging in mind. We report device-level measurements of key components and validate comb-driven end-to-end data

Aug 08, 2025

1.6 Tbps FOWLP-Based Silicon Photonic Engine for Co-Packaged

Co-packaged optics (CPO) has emerged as a promising solution to address the limitations of traditional pluggable optical transceivers, offering enhanced bandwidth, improved

Dec 19, 2025

Sample Pages

Co-packaged photonics, particularly for network switches and compute silicon with topside package interconnects, can alleviate the demand on socket pins in HPC systems.

Dec 01, 2025

CPO Article_EPS_2023_SR_Final

This allows for cost effective, scalable mass production of photonics interconnects that can also enable co-packaging with ASICs (or CPUs/GPUs) using semiconductor packaging &

Apr 10, 2026

Heterogeneous Integration Technology Drives the

The rapid growth of artificial intelligence (AI), data centers, and high-performance computing (HPC) has increased the demand for large bandwidth,

Mar 31, 2026

Broadcom CPO: Highest Power Efficiency and

Co-Packaged Optics (CPO) is an advanced integration of optics and silicon on a single packaged substrate addressing interconnect bandwidth and

Apr 25, 2026

Co-packaged Optics | Springer Nature Link

Co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE)

Aug 15, 2025

Designing Co-Packaged Optics (CPO) with Ansys

Ansys is a dedicated collaboration partner for the development and continuous improvement of leading-edge multi-physics and multi-scale workflows for optical/photonic components and systems.

Jul 16, 2025

arXiv e-Print archive

The paper discusses future advancements in silicon photonics technology.

Mar 01, 2026

[2503.02712] Low-Loss Integration of High-Density Polymer

Co-Packaged Optics applications require scalable and high-yield optical interfacing solutions to silicon photonic chiplets, offering low-loss, broadband, and polarization-independent

Oct 30, 2025

Co-Packaged Optics — a deep dive | APNIC Blog

However, electrical-optical-electrical conversions consume significant power for any photonic connectivity. If alternative approaches for ultra-large

Nov 08, 2025

Selection Guide for Co-packaged Photonics QSFP-DD for Wind

This guide explains how to choose QSFP-DD transceivers step by step, helping you avoid costly mistakes and ensure compatibility across your network. Before selecting reach or connector type,

Mar 07, 2026

Scaling Co-Packaged Optical Interconnects Using Hybrid 2.5D/3D

We describe a novel system which uses hybrid 2.5D/3D integration to compose a state-of-the-art FPGA compute chiplet, three electrical interface chiplets, and three photonic interface chiplets.

May 25, 2026

Silicon-Photonics-Embedded Interposers as Co-Packaged Optics

ceiver is the most promising candidate for use in co-packaged optics. Since Si-photonics technologies miniaturize optical circuits and integrate them with electronic circuits on a Si die, it is advantageous

Apr 29, 2026

Co-Packaged Optics for Datacenter

Challenges for Co-Packaged Optics Technical issues are not insurmountable, but integration is the issue Ecosystem needs to be established, including design capabilities No standard PDK for Si fab,

Jun 28, 2026

Co‐packaged datacenter optics: Opportunities and

The increased escape bandwidth offered by co-packaged optics provides multiple possibilities for building 50T switches and beyond, expanding

Sep 02, 2025

Next generation Co-Packaged Optics Technology to Train & Run

Module Co-Design & Modeling A co-packaged optic module design was developed to support electronic and optics compatibility, industry standards where applicable and scaling for design, process,

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